As the speed/bandwidth at which the input-output (I/O) circuits operate is increasing, circuits associated with such I/Os become sensitive to duty cycle and voltage swings of associated signals. Timing uncertainty of high speed clock signals, including power supply induced jitter and clock duty cycle error caused by mismatch between adjacent transistors arising from manufacturing variations, limit the overall operating data rate of high speed serial I/Os. To overcome such limitation in overall operating data rate, low signal swing clock signals are used for I/O circuits because such low swing signals are more robust against power supply induced jitter. These low signal swing signals are called Current-Mode-Logic (CML) level signals. CML level signals generally operate at voltage swings which are around 30-40% of the full power supply rail/voltage level.
However the end use point of these clock signals is usually CMOS level logic circuits, requiring rail-to-rail voltage swings. Some circuits provide better performance via CMOS level signals with a 50% duty cycle. A signal with 50% duty cycle is a signal that remains high and low for the same duration of time in a signal period. A signal with more than 50% duty cycle is a signal that has a longer high pulse than its corresponding low pulse in a signal period. Similarly, a signal with less than 50% duty cycle is a signal that has a longer low pulse than its corresponding high pulse in a signal period.
For such circuits that require CMOS level signals, the CML level signals are converted to CMOS level signals, which are rail-to-rail signals, at the input of these circuits. For example, transmitters and receivers of Peripheral Component Interconnect Express (PCIe) I/O circuits require CMOS level signals with 50% duty cycle and reduced signal jitter for proper operation at high frequencies (e.g., 4 GHz and above). These CML to CMOS level signal converters introduce performance limiting characteristics to the output CMOS level signals. Examples of performance limiting characteristics include higher power consumption, lower timing margin, non-50% duty cycle, increased jitter amplification, power supply induced jitter, etc.